Test Optimization in Production through the Use of Boundary Scan

View our latest webinar recording on “Test Optimization in Production – Reduction of Test Time through the Use of Boundary Scan” to learn how you can reduce test time and complex interface hardware through the use of JTAG/Boundary Scan. While Boundary Scan as a test methodology has been around for more than 25 years, its advantages for production test often are still underestimated.
And, over the years this technology has seen a lot of innovation.

Designers and test planners alike are confronted with the same problem: to ensure sufficient test access despite increasing miniaturization and simultaneous increase in functionality and complexity of modern electronics.
“Every circuit node needs a test point!” Many of you have heard this statement. But this is no longer possible on modern electronics. Join us in this webinar to learn about powerful and cost saving methods to utilize boundary-scan and related technologies in manufacturing test.

Topics that will be addressed during the webinar:

  • “JTAG / Boundary Scan” nowadays is much more than just connectivity test.
  • Utilize the UUT’s FPGA or microprocessor as an embedded test system.
  • Testing that previously required high numbers of test probes can still be done when physical external access is no longer possible.

 

Target audience:  Test engineers, test managers, production engineers, production managers, CEOs, contract designers and contract manufacturers, design engineers and design managers.

 

Level:  Beginners and advanced users.

 

This webinar was originally presented on November 3, 2015.

Feel free to view the webinar recording by following this link

GOEPEL presents Embedded System Access (ESA) Technology at ITC 2015

Key elements of current & future Application Specific Standard Product (ASSP) designs include large, fast memory, (multi-) core processors, wired and/or wireless networking, high-speed communication interfaces, graphical control and display features, as well as sensors and actors (MEMS). All of these elements require advanced test techniques, if for no other reasons than diminishing test access:

paradigm change - transparent

 

GOEPEL presents a number of test techniques under the umbrella of Embedded System Access (ESA) technologies at this year’s International Test Conference (ITC) in Anaheim, CA. Visit us at booth #219 to learn more about technologies for high-speed memory test, high-speed in-system programming, FPGA assisted testing, processor emulation test, and embedded real-time diagnostics.

High-speed programming with RAPIDO

This short video shows RAPIDO in action: high-speed programming on up to 32 boards in parallel. For more details, visit http://www.goepelusa.com/model/rapido/.

 

This video has been recorded at electronica 2014 in Munich, Germany, demonstrating high-speed in-system programming and boundary-scan testing of ten boards in parallel. In actual use, RAPIDO would be used in-line in the manufacturing environment.

Details and product brief can be found on GOEPEL’s website. Or, simply send us your inquiry.

New mixed-signal JTAG I/O module

CION LX module FXT96

CION LX module FXT96

At International Test Conference (ITC) 2014 in Seattle, GOEPEL Electronics introduced the CION-LX Module/FXT96, a new mixed-signal JTAG I/O module enabling boundary-scan based tests to non scannable circuit components such as connectors, clusters, or analog interfaces.

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SCANVISION III Layout and Schematic Visualization in CASCON GALAXY

Watch this short video to get a brief overview of some of the SCANVISION tools and features available in GOEPEL’s CASCON GALAXY software. SCANVISION is a software tool for the visualization of layout and schematic files for printed circuit board assemblies, tightly integrated in the JTAG / boundary-scan software environment CASCON GALAXY.

 

To learn more about SCANVISION or other tools in CASCON GALAXY, please visit www.goepelusa.com or contact us.