SJTAG starts activities as IEEE sponsored study group

The SJTAG initiative has been granted Study Group status by IEEE’s TTSC. Please join the study group if you are interested in the prospect of standardizing system test access management.

Call for participation:

 

This is a call for participation in the “System Test Access Management” Study Group (also referred to as ‘SJTAG’). Those interested in joining the study group or being kept informed of its activities should notify their interest by email to chair@sjtag.org or via the group’s Contact Page (http://www.sjtag.org/members/contact-us).

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Everything you need to know about embedded real-time functional test

Can you imagine an embedded diagnostic operating system suitable for use in lab and production; capable of performing both at-speed / real-time diagnostic functional tests and high-speed in-system flash programming?

Intrigued? Attend our upcoming webinar on January 26th, at 11 AM EST, 8 AM PST (16:00 UTC).

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Test Optimization in Production through the Use of Boundary Scan

View our latest webinar recording on “Test Optimization in Production – Reduction of Test Time through the Use of Boundary Scan” to learn how you can reduce test time and complex interface hardware through the use of JTAG/Boundary Scan. While Boundary Scan as a test methodology has been around for more than 25 years, its advantages for production test often are still underestimated.
And, over the years this technology has seen a lot of innovation.

Designers and test planners alike are confronted with the same problem: to ensure sufficient test access despite increasing miniaturization and simultaneous increase in functionality and complexity of modern electronics.
“Every circuit node needs a test point!” Many of you have heard this statement. But this is no longer possible on modern electronics. Join us in this webinar to learn about powerful and cost saving methods to utilize boundary-scan and related technologies in manufacturing test.

Topics that will be addressed during the webinar:

  • “JTAG / Boundary Scan” nowadays is much more than just connectivity test.
  • Utilize the UUT’s FPGA or microprocessor as an embedded test system.
  • Testing that previously required high numbers of test probes can still be done when physical external access is no longer possible.

 

Target audience:  Test engineers, test managers, production engineers, production managers, CEOs, contract designers and contract manufacturers, design engineers and design managers.

 

Level:  Beginners and advanced users.

 

This webinar was originally presented on November 3, 2015.

Feel free to view the webinar recording by following this link

GOEPEL presents Embedded System Access (ESA) Technology at ITC 2015

Key elements of current & future Application Specific Standard Product (ASSP) designs include large, fast memory, (multi-) core processors, wired and/or wireless networking, high-speed communication interfaces, graphical control and display features, as well as sensors and actors (MEMS). All of these elements require advanced test techniques, if for no other reasons than diminishing test access:

paradigm change - transparent

 

GOEPEL presents a number of test techniques under the umbrella of Embedded System Access (ESA) technologies at this year’s International Test Conference (ITC) in Anaheim, CA. Visit us at booth #219 to learn more about technologies for high-speed memory test, high-speed in-system programming, FPGA assisted testing, processor emulation test, and embedded real-time diagnostics.

GOEPELUSA.com Redesigned

As you may have noticed, we have redesigned our website www.goepelusa.com.

While we think that the new design is a vast improvement, and new features such as the product finder, site search, and site wide registration for downloads will be very useful, we are keen to hear from you and get feedback about what you think of the redesign and of the content of our website.
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