Test Strategy for IoT Devices receives Embedded World 2016 Award

embedded Award 2016At Embedded World 2016 in Nuremberg, JEDOS (GOEPEL’s test and diagnostics tool for electronic assemblies) received the embedded Award 2016 in the tools category.

With the Embedded Award, a high-ranking jury with representatives from science research, industry, and media recognizes innovative products and solutions that advance the industry of embedded systems and the IoT (Internet of Things) in outstanding ways. GOEPEL receives Embedded Award 2016
The award ceremony took place at the official press conference by Prof. Matthias Sturm, Chairman of the Advisory Board of the embedded world, and Dr. Roland Fleck, Managing Director of NürnbergMesse on the first day of Embedded World.

“We are proud of the high recognition our JEDOS test and diagnostic tool enjoys. Winning this award shows us that with our integrated technology platform we’re on the right track”, says Thomas Wenzel, Managing Director of the JTAG/Boundary Scan division of GOEPEL electronic, after accepting the award. JEDOS awarded at Embedded World 2016“By integrating embedded diagnostics test and JTAG/boundary scan, we are addressing the latest test challenges posed by complex electronic designs, such as Internet of Things components.”

First introduced in 2015, JEDOS is a platform for high-quality embedded tests of complex electronic design. JEDOS offers a variety of functions for test, validation, calibration, and device programming. Using the native processor, diagnostic functional tests can be performed in real time. A key advantage of JEDOS is the possibility to fully test IoT components without the use of firmware. By integrating of boundary scan and functional embedded test and diagnostics, dependable test and fault coverage can be achieved. As a result, firmware and software engineers can benefit from pre-verified prototype hardware, making their development and debug work more efficient.

To learn more about JEDOS, please view this webinar or contact GOEPEL.

Test Optimization in Production through the Use of Boundary Scan

View our latest webinar recording on “Test Optimization in Production – Reduction of Test Time through the Use of Boundary Scan” to learn how you can reduce test time and complex interface hardware through the use of JTAG/Boundary Scan. While Boundary Scan as a test methodology has been around for more than 25 years, its advantages for production test often are still underestimated.
And, over the years this technology has seen a lot of innovation.

Designers and test planners alike are confronted with the same problem: to ensure sufficient test access despite increasing miniaturization and simultaneous increase in functionality and complexity of modern electronics.
“Every circuit node needs a test point!” Many of you have heard this statement. But this is no longer possible on modern electronics. Join us in this webinar to learn about powerful and cost saving methods to utilize boundary-scan and related technologies in manufacturing test.

Topics that will be addressed during the webinar:

  • “JTAG / Boundary Scan” nowadays is much more than just connectivity test.
  • Utilize the UUT’s FPGA or microprocessor as an embedded test system.
  • Testing that previously required high numbers of test probes can still be done when physical external access is no longer possible.

 

Target audience:  Test engineers, test managers, production engineers, production managers, CEOs, contract designers and contract manufacturers, design engineers and design managers.

 

Level:  Beginners and advanced users.

 

This webinar was originally presented on November 3, 2015.

Feel free to view the webinar recording by following this link

GOEPEL presents Embedded System Access (ESA) Technology at ITC 2015

Key elements of current & future Application Specific Standard Product (ASSP) designs include large, fast memory, (multi-) core processors, wired and/or wireless networking, high-speed communication interfaces, graphical control and display features, as well as sensors and actors (MEMS). All of these elements require advanced test techniques, if for no other reasons than diminishing test access:

paradigm change - transparent

 

GOEPEL presents a number of test techniques under the umbrella of Embedded System Access (ESA) technologies at this year’s International Test Conference (ITC) in Anaheim, CA. Visit us at booth #219 to learn more about technologies for high-speed memory test, high-speed in-system programming, FPGA assisted testing, processor emulation test, and embedded real-time diagnostics.

New mixed-signal JTAG I/O module

CION LX module FXT96

CION LX module FXT96

At International Test Conference (ITC) 2014 in Seattle, GOEPEL Electronics introduced the CION-LX Module/FXT96, a new mixed-signal JTAG I/O module enabling boundary-scan based tests to non scannable circuit components such as connectors, clusters, or analog interfaces.

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GOEPEL and SiliconAid join forces to provide Chip Level Debug in Board and System Environments

GOEPEL Electronics announces joint developments with SiliconAid Solutions in the area of chip level debug in board and system environments. GOEPEL and SiliconAid personnel were present at ITC in Anaheim, CA, last week to discuss details of these developments and the benefits of leveraging both technologies together.

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