View our latest webinar recording on “Test Optimization in Production – Reduction of Test Time through the Use of Boundary Scan” to learn how you can reduce test time and complex interface hardware through the use of JTAG/Boundary Scan. While Boundary Scan as a test methodology has been around for more than 25 years, its advantages for production test often are still underestimated.
And, over the years this technology has seen a lot of innovation.
Designers and test planners alike are confronted with the same problem: to ensure sufficient test access despite increasing miniaturization and simultaneous increase in functionality and complexity of modern electronics.
“Every circuit node needs a test point!” Many of you have heard this statement. But this is no longer possible on modern electronics. Join us in this webinar to learn about powerful and cost saving methods to utilize boundary-scan and related technologies in manufacturing test.
Topics that will be addressed during the webinar:
“JTAG / Boundary Scan” nowadays is much more than just connectivity test.
Utilize the UUT’s FPGA or microprocessor as an embedded test system.
Testing that previously required high numbers of test probes can still be done when physical external access is no longer possible.
Target audience: Test engineers, test managers, production engineers, production managers, CEOs, contract designers and contract manufacturers, design engineers and design managers.
Level: Beginners and advanced users.
This webinar was originally presented on November 3, 2015.
At International Test Conference (ITC) 2014 in Seattle, GOEPEL Electronics introduced the CION-LX Module/FXT96, a new mixed-signal JTAG I/O module enabling boundary-scan based tests to non scannable circuit components such as connectors, clusters, or analog interfaces.
Traditionally, the JTAG interface has been used for board-level testing based on the Std. IEEE 1149.1 (also known as Boundary Scan). The standard was first adopted in the early 90’s and since then, the JTAG interface has morphed into an interface that is not only used for test purposes. Furthermore, not all applications utilized over JTAG have been standardized as has been done Std IEEE 1149.1. The broad range of applications made possible over the JTAG interface have introduced new challenges for compatibility; many applications using the JTAG interface may not be fully compliant with IEEE Std 1149.1 unless special measures are taken into consideration.
JTAG / boundary-scan features are implemented in many digital circuits, with one glaring exception: a majority of memory devices do not support IEEE Std 1149.1. The connectivity between a boundary-scan compliant components and such memory devices can then only be tested by means of cluster testing: writing to the memory and reading back pattern written to the memory (while some memory devices may have test modes, often times those test modes are permanently disabled in the board design – not a good thing; board test engineers generally prefer device test modes to be accessible at board and system level).
When most test or design engineers hear “JTAG”, many things may come to mind. The acronym itself stands for Joint Test Action group — a user group who initialized the IEEE 1149.1 standard, also known as boundary scan. However, since its inception as the first sanctioned IEEE test standard, JTAG has evolved to embody a variety of applications not included in the originally drafted IEEE 1149.1 standard. Nowadays, the JTAG term is not very straightforward and often ambiguous. Today, the JTAG interface is utilized for a range of applications.